引用次数
引用: 6,857
H-指数: 36
I10-指数 : 78
出版物: 197
VELOCITY OVERSHOOT OF ELECTRONS AND HOLES, IN
D SINITSKY , F ASSADERAGHI , M ORSHANSKY , J BOKOR
1997
An accurate sparse-matrix based framework for statistical static timing analysis: ON ADVANCES IN TIMING
Anand RAMALINGAM , Ashish KUMAR SINGH , Sani R NASSIF , Gi-Joon NAM
Integration (Amsterdam) 45 ( 4) 365 -375
2012
Static Timing Analysis Based on Partial Probabilistic Description of Delay Uncertainty
Michael Orshansky , Wei-Shen Wang , Vladik Kreinovich
1
2006
Design for Manufacturability and Statistical Design: A Constructive Approach
Michael Orshansky , Duane Boning , Sani Nassif
293
2007
Logic synthesis for reducing leakage power consumption under workload uncertainty
Michael Orshansky , Ashish K. Singh
international conference on circuits 351 -355
2008
Electrically driven optical proximity correction based on linear programming
Michael Orshansky , Lars W. Liebmann , Praveen Elakkumanan , Shayak Banerjee
international conference on computer aided design 473 -479
16
2008
Variable-energy write STT-RAM architecture with bit-wise write-completion monitoring
Michael Orshansky , Mattan Erez , Tianhao Zheng , Jaeyoung Park
international symposium on low power electronics and design 229 -234
42
2013
Multi-level approximate logic synthesis under general error constraints
Andreas Gerstlauer , Michael Orshansky , Jin Miao
international conference on computer aided design 504 -510
32
2014
An algorithm for exploiting modeling error statistics to enable robust analog optimization
Michael Orshansky , Constantine Caramanis , Kareem Ragab , Ashish Kumar Singh
international conference on computer aided design 62 -69
4
2010
Approximate logic synthesis under general error magnitude and frequency constraints
Andreas Gerstlauer , Michael Orshansky , Jin Miao
international conference on computer aided design 779 -786
54
2013
Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits
Linda Milor , Michael Orshansky , Kurt Keutzer , Pinhong Chen
international conference on computer aided design 62 -67
80
2000
A methodology for propagating design tolerances to shape tolerances for use in manufacturing
Shayak Banerjee , Kanak B Agarwal , Chin-Ngai Sze , Sani Nassif
design, automation, and test in europe 1273 -1278
4
2010
Efficient simulation of EM side-channel attack resilience
Michael Orshansky , Ali Yilmaz , Cody Scarborough , Amit Kumar
international conference on computer aided design 123 -130
10
2017
Training with Multi-Layer Embeddings for Model Reduction
Michael Orshansky , Mattan Erez , Ashish Kumar Singh , Benjamin Y. Cho
arXiv: Learning
6
2020
Galvanically Isolated, Power and Electromagnetic Side-Channel Attack Resilient Secure AES Core with Integrated Charge Pump based Power Management
Meizhi Wang , Michael Orshansky , Aseem Sayal , Ali E. Yilmaz
custom integrated circuits conference 1 -2
2021
Physical Design Strategies for Mitigating Fine-Grained Electromagnetic Side-Channel Attacks
Michael Orshansky , Sanu K. Mathew , Ali E. Yilmaz , Raghavan Kumar
custom integrated circuits conference 1 -2
2021
Circuit-Level Timing-Error Acceptance for Design of Energy-Efficient DCT/IDCT-Based Systems
Ku He , Andreas Gerstlauer , Michael Orshansky
IEEE Transactions on Circuits and Systems for Video Technology 23 ( 6) 961 -974
19
2013
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
David Nguyen , Abhijit Davare , Michael Orshansky , David Chinnery
Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03 158 -163
208
2003
Fast statistical timing analysis handling arbitrary delay correlations
Michael Orshansky , Arnab Bandyopadhyay
design automation conference 337 -342
109
2004
A sequence dependent challenge-response PUF using 28nm SRAM 6T bit cell
Supreet Jeloka , Kaiyuan Yang , Michael Orshansky , Dennis Sylvester
symposium on vlsi circuits
55
2017