Venkata Rajesh Pamula
机构: University of Washington Seattle
每年引用次数
引用次数
引用: 606
H-指数: 14
I10-指数 : 18
出版物: 48
22.4 A 172µW compressive sampling photoplethysmographic readout with embedded direct heart-rate and variability extraction from compressively sampled data
Pamula Venkata Rajesh , Jose Manuel Valero-Sarmiento , Long Yan , Alper Bozkurt
international solid-state circuits conference 59 386 -387
34
2016
PHIDIAS
D Bortolotti , G Ansaloni , D Atienza , P Vandergheynst
Proceedings of the ACM International Conference on Computing Frontiers-CF'16
A 0.0023 mm $^ 2$/ch. Delta-Encoded, Time-Division Multiplexed Mixed-Signal ECoG Recording Architecture With Stimulus Artifact Suppression
John P Uehlin , William Anthony Smith , V Rajesh Pamula , Steve I Perlmutter
IEEE transactions on biomedical circuits and systems 14 ( 2) 319 -331
39
2019
Exploiting System Configurability towards Dynamic Accuracy-Power Trade-offs in Sensor Front-ends
Laura Isabel Galindez Olascoaga , Komail Badami , V Rajesh Pamula , Steven Lauwereins
2016 50TH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS 1027 -1031
2016
Exploiting system configurability towards dynamic accuracy-power trade-offs in sensor front-ends
O Laura I Galindez , Komail Badami , V Rajesh Pamula , Steven Lauwereins
2016 50th Asilomar Conference on Signals, Systems and Computers 1027 -1031
3
2016
F. u. Rahman, B. Zhang, VS Sathe," A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction,"
VR Pamula , X Sun , SM Kim
IEEE Solid-State Circuits Letters 1 ( 12) 237 -240
5
2018
Guest Editorial—Selected Papers from the 2014 IEEE International Solid-State Circuits Conference.....................
KH Chang , TH Chang , CM Wang , CL Chang
Analog-and-Algorithm-Assisted Ultra-low Power Biosignal Acquisition Systems
Venkata Rajesh Pamula , Marian Verhelst , Chris Van Hoof
1
2019
Model Based Development of the Digital Part of a RFID Transponder with Xilinx System Generator for a FPGA Platform
Venkata Rajesh Pamula , Wolfram Strauss , Josef Bernhard
2012 Fourth International EURASIP Workshop on RFID Technology 124 -127
1
2012
A 65-nm CMOS 3.2-to-86 Mb/s 2.58 pJ/bit Highly Digital True-Random-Number Generator With Integrated De-Correlation and Bias Correction
Venkata Rajesh Pamula , Xun Sun , Sung Min Kim , Fahim ur Rahman
IEEE Solid-State Circuits Letters 1 ( 12) 237 -240
3
2018
A Wearable Wrist-Band with Compressive Sensing based Ultra-Low Power Photoplethysmography Readout Circuit
Parvez Ahmmed , James Dieffenderfer , Jose Manuel Valero-Sarmiento , Venkata Rajesh Pamula
wearable and implantable body sensor networks 1 -4
2
2019
An All-Digital Fused PLL-Buck Architecture for 82% Average V dd -Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor
Xun Sun , Fahim ur Rahman , Venkata Rajesh Pamula , Sung Kim
IEEE Journal of Solid-state Circuits 54 ( 11) 3215 -3225
2019
A Single-Chip Bidirectional Neural Interface With High-Voltage Stimulation and Adaptive Artifact Cancellation in Standard CMOS
John P. Uehlin , William Anthony Smith , Venkata Rajesh Pamula , Eric P. Pepin
IEEE Journal of Solid-State Circuits 55 ( 7) 1749 -1761
1
2020
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor
Xun Sun , Sung Kim , Fahim ur Rahman , Venkata Rajesh Pamula
2018 IEEE International Solid - State Circuits Conference - (ISSCC) 302 -304
10
2018
14.5 A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS
Xun Sun , Akshat Boora , Wenbing Zhang , Venkata Rajesh Pamula
international solid-state circuits conference 230 -232
9
2019
A Bidirectional Brain Computer Interface with 64-Channel Recording, Resonant Stimulation and Artifact Suppression in Standard 65nm CMOS
John Uehlin , William Anthony Smith , Venkata Rajesh Pamula , Steve Perlmutter
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) 77 -80
1
2019
An Ultra-low Power, Robust Photoplethysmographic Readout Exploiting Compressive Sampling, Artifact Reduction, and Sensor Fusion
Venkata Rajesh Pamula , Chris Van Hoof , Marian Verhelst
Hybrid ADCs, Smart Sensors for the IoT, and Sub-1V & Advanced Node Analog Circuit Design 145 -163
3
2018
A 680 nA ECG Acquisition IC for Leadless Pacemaker Applications
Long Yan , Pieter Harpe , Venkata Rajesh Pamula , Masato Osawa
IEEE Transactions on Biomedical Circuits and Systems 8 ( 6) 779 -786
28
2014
A 172 $\mu$W Compressively Sampled Photoplethysmographic (PPG) Readout ASIC With Heart Rate Estimation Directly From Compressively Sampled Data
Venkata Rajesh Pamula , Jose Manuel Valero-Sarmiento , Long Yan , Alper Bozkurt
IEEE Transactions on Biomedical Circuits and Systems 11 ( 3) 487 -496
10
2017
Improving SIMO-regulated digital SoC energy efficiencies through adaptive clocking and concurrent domain control
Chi-Hsiang Huang , Yidong Chen , Xun Sun , Arindam Mandal
IEEE Journal of Solid-State Circuits 57 ( 1) 90 -102
3
2021