Hemangee K Kapoor
机构: Indian Institute of Technology Guwahati
每年引用次数
引用次数
引用: 726
H-指数: 14
I10-指数 : 24
出版物: 148
Specification and Analysis of NCL Circuits.
J Ma , HK Kapoor , Tomas Krilavičius , Ka Lok Man
Engineering Letters 19 ( 3)
2
2011
Genetic stocks of Kashmir Papavers: 1. Plant morphology, chromosome numbers and meioses
AK Koul , RN Gohil , MC Sharma , HK Kapoor
Nucleus 15 ( 2) 117 -123
4
1972
FORMAL MODELLING AND VERIFICATION OF COMPENSATING WEB TRANSACTIONS
SHIRSHENDU DAS , SHOUNAK CHAKRABORTY , HEMANGEE K. KAPOOR , KA LOK MAN
WORLD SCIENTIFIC 123 -136
2013
Formal Verification and Synthesis Of Null Conventional Logic Circuits
HEMANGEE K. KAPOOR , JIEMING MA , TOMAS KRILAVIČIUS , KA LOK MAN
international multiconference of engineers and computer scientists 320 -333
2012
WELCOMF: Wear leveling assisted compression using frequent words in non-volatile main memories
Arijit Nath , Hemangee K Kapoor
Smpte Journal 157 -162
5
2020
CCGRID 2023: A Holistic Approach to Inclusion and Belonging
Beth Plale , Preeti Malakar , Meenakshi D'Souza , Hemangee K Kapoor
2023 IEEE/ACM 23rd International Symposium on Cluster, Cloud and Internet Computing (CCGrid) 684 -685
2023
13th International Workshop on Network on Chip Architectures (NoCArc)
Avijit Chakraborty , Carmen Almudéver , Danella Zhao , Diana Göhringer
Increasing Diversity, Equity, and Inclusion Awareness: An Example from India
Hemangee K Kapoor , David A Patterson
Communications of the ACM 67 ( 4) 35 -36
2024
VLSID 2019
Sumana Ghosh , Soumyajit Dey , Khushboo Rani , Hemangee K Kapoor
Hydra: A near hybrid memory accelerator for CNN inference
Palash Das , Ajay Joshi , Hemangee K Kapoor
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE) 1017 -1022
3
2022
Lifetime enhancement of non-volatile caches by exploiting dynamic associativity management techniques
Sukarn Agarwal , Hemangee K Kapoor
VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things: 25th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23–25, 2017, Revised and Extended Selected Papers 24 46 -71
3
2019
Didasel: Dirty data based selection of vc for effective utilization of nvm buffers in on-chip interconnects
Khushboo Rani , Sukarn Agarwal , Hemangee K Kapoor
151 -156
1
2020
Towards a language based synthesis of ncl circuits
Hemangee K Kapoor , Abhinav Asthana , Tomas Krilavicius , Wenjie Zeng
Proceedings of the 2011 International MultiConference of Engineers and Computer Scientists 1033 -1038
5
2011
Modelling and verification of compensating transactions using the Spin tool
Kaiyu Wan , Hemangee K Kapoor , Shirshendu Das , B Raju
Engineers and computer scientists: IMECS: proceedings of the international Multiconference 14 -16
4
2012
Performance improvement by N-chance clustered caching in NoC based chip multi-processors
Rakesh Yarlagadda , Sanmukh R Kuppannagari , Hemangee K Kapoor
Architecture (NUCA) 3 4 -4
3
2011
CORIDOR: Using CO herence and Tempo R al Local I ty to Mitigate Read D isurbance Err OR in STT-RAM Caches
Sheel Sindhu Manohar , Sparsh Mittal , Hemangee K Kapoor
ACM Transactions on Embedded Computing Systems (TECS) 21 ( 1) 1 -24
2
2022
Formal approach for DVS-based power management for multiple server system in presence of server failure and repair
Lalit Chandnani , Hemangee K Kapoor
IEEE Transactions on Industrial Informatics 9 ( 1) 502 -513
12
2012
A process algebraic view of latency-insensitive systems
Hemangee K Kapoor
IEEE Transactions on Computers 58 ( 7) 931 -944
9
2008
Cache capacity and its effects on power consumption for tiled chip multi-processors
Shounak Chakraborty , Dipika Deb , Dhantu Buragohain , Hemangee K Kapoor
2014 International Conference on Electronics and Communication Systems (ICECS) 1 -6
7
2014
CAPMIG: Coherence-aware block placement and migration in multiretention STT-RAM caches
Sheel Sindhu Manohar , Hemangee K Kapoor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 42 ( 2) 411 -422
5
2022