引用次数
引用: 16,026
H-指数: 68
I10-指数 : 145
出版物: 233
28nm metal-gate high-K CMOS SoC technology for high-performance mobile applications
S.H. Yang , J.Y. Sheu , M.K. Ieong , M.H. Chiang
custom integrated circuits conference 1 -5
18
2011
Construction of higher‐moment terms in the hydrodynamic electron‐transport model
D. L. Woolard , H. Tian , M. A. Littlejohn , K. W. Kim
Journal of Applied Physics 74 ( 10) 6197 -6207
15
1993
Distributed Algorithms for Three-dimensional Semiconductor Device Simulations
Mei-Kei Ieong , Ting-Wei Tang
Vlsi Design 6 123 -126
1998
Quasi self-aligned source/drain FinFET process
Mei-Kei Ieong , Thomas Ludwig , Edward J Nowak , Qiqing C Ouyang
134
2007
A general hydrodynamic solver for deep submicron silicon devices
Mei-Kei Ieong , Tw Tang
Proc. Int. Workshop on Computational Electronics 111 -114
3
1994
Sub-30 NM abrupt junction formation in strained silicon/silicon-germanium CMOs device
J. Chu , H. Zhu , K. Chan , P. Saunders
International symposium on advanced short-time thermal processing for si-based CMOS devices II 71 -81
2004
Recent progress in devices and materials for CMOS technology
H.-S.P. Wong , B. Doris , E. Gusev , M. Ieong
international symposium on vlsi technology systems and applications 13 -16
3
2003
Ultra-Thin SOI CMOS Using Laser Spike Anneal
Zhibin Ren , J. Sleight , J. Hergenrother , D. Singh
international symposium on vlsi technology, systems, and applications 1 -2
2006
A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET
R. Young , L. Su , M. Ieong , S. Kapur
IEEE Electron Device Letters 19 ( 7) 234 -236
8
1998
Process induced stress for CMOS performance improvement
S. Fang , S. Tan , T. Dyer , Z. Luo
international conference on solid state and integrated circuits technology 108 -111
1
2006
Uniaxial strain relaxation on ultra-thin strained-Si directly on insulator (SSDOI) substrates
Haizhou Yin , Z. Ren , K.L. Saenger , H.J. Hovel
international conference on solid state and integrated circuits technology 136 -138
9
2006
Dual stress liner enhancement in hybrid orientation technology
C.D. Sheraw , M. Yang , D.M. Fried , G. Costrini
symposium on vlsi technology 12 -13
38
2005
Mobility and CMOS devices/circuits on sub-10nm [110] ultra thin body SOI
H. Shang , J. Rubino , B. Doris , A. Topol
symposium on vlsi technology 78 -79
11
2005
Effect of tensile uniaxial stress on the electron transport properties of deeply scaled FD-SOI n-type MOSFETs
H.M. Nayfeh , D.V. Singh , J.M. Hergenrother , J.W. Sleight
IEEE Electron Device Letters 27 ( 4) 288 -290
11
2006
Strained ultrahigh performance fully depleted nMOSFETs with f/sub t/ of 330 GHz and sub-30-nm gate lengths
D.V. Singh , K.A. Jenkins , J. Sleight , Z. Ren
IEEE Electron Device Letters 27 ( 3) 191 -193
20
2006
Self-Aligned n-Channel Germanium MOSFETs With a Thin Ge Oxynitride Gate Dielectric and Tungsten Gate
H. Shang , K.-L. Lee , P. Kozlowski , C. D'Emic
IEEE Electron Device Letters 25 ( 3) 135 -137
208
2004
Low Tinv (≤ 1.8 nm) Metal-Gated MOSFETs on SiO2 Based Gate Dielectrics for High Performance Logic Applications
V. Ku , R. Amos , A. Steegen , C. Cabral
Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials
3
2003
Strained Si CMOS (SS CMOS) technology: Opportunities and challenges
K. Rim , R. Anderson , D. Boyd , F. Cardone
Solid-state Electronics 47 ( 7) 1133 -1139
80
2003
Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)
A.W. Topol , D.C. La Tulipe , L. Shi , S.M. Alam
international electron devices meeting 352 -355
120
2005
Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths
D.V. Singh , J.W. Sleight , J.M. Hergenrother , Z. Ren
international electron devices meeting 505 -508
23
2005