Coprocessor with dataflow circuitry controlling sequencing to execution unit of data received in tokens from master processor
作者： Yukio Maehashi , Masahiro Nomura
DOI:
关键词: Execution unit 、 Application-specific instruction-set processor 、 Computer hardware 、 Information processor 、 Coprocessor 、 Computer architecture 、 Computer science 、 Dataflow architecture 、 Pipeline burst cache 、 Media processor 、 Processor affinity
摘要: An information processing apparatus with a dual processor system contains general purpose for required program and special specific operation in the program. The is designed according to data flow architecture executes task token prepared by processor, having sequence control be processed. employed enables placement of both single on semiconductor chip, also asynchronous, parallel two processors.
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