Design of Reusable VHDL Component Using External Functions

摘要: This paper describes a method how to represent and build reusable VHDL component. By that component we can, for example, describe family of the relative models. To component, use external functions as mechanism support pre-processing perform instantiation A user interface, constituent serves transferring parameters instantiation. We deliver formal syntax examples their semantics. design procedure of: a) intrinsic characteristics given domain objects b) features from model(s). Those require be re-coded extended with new ones by means introduced. test modelling.