CLOCK CONTROL CIRCUIT
作者： Iwami Koichi
DOI:
关键词: State (computer science) 、 Delay time 、 Gate control 、 Logic level 、 Clock control 、 Clock signal 、 Reset (computing) 、 Electrical engineering 、 Signal 、 Computer science
摘要: PROBLEM TO BE SOLVED: To provide a clock control circuit which stops signal or reduces frequency before after state of with large delay time changes. SOLUTION: The includes: gate 1 supply the signal; and 13 by in response to reset signal, generates an internal whose logic level changes Consequently, malfunctions flip-flops 21-25 are prevented. COPYRIGHT: (C)2011,JPO&INPIT
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