A high throughput pipelined hardware architecture for tag sorting in packet fair queuing schedulers
作者： Nguyen Van Tu , Vu Tang Thien , Son Nguyen Kim , Nam Pham Ngoc , Thanh Nguyen Huu
DOI: 10.1109/COMMANTEL.2015.7394257
关键词: Scheduling (computing) 、 Virtex 、 Embedded system 、 Clock rate 、 Computer science 、 Network packet 、 Field-programmable gate array 、 Sorting 、 Hardware architecture 、 Throughput (business) 、 Network scheduler 、 Fair queuing
摘要: In a timestamp-base packet scheduler, which is an important part of Quality Service (QoS) enabled network systems, Tag Sorting the most critical step. This paper presents high throughput pipelined architecture for targeting FPGA technology. Our implementation results on Xilinx Virtex II pro 50 chip have shown that our design can run at maximum clock frequency 216 MHz and process one tag every 2 cycles, thus provides 108 million tags per second support 100 Gbps line speeds.
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