作者: Richard Alexander Erhart
DOI:
关键词: Pass transistor logic 、 Ground bounce 、 Static induction transistor 、 Field-effect transistor 、 Electrical engineering 、 Multiple-emitter transistor 、 Engineering 、 Drain-induced barrier lowering 、 Threshold voltage 、 Overdrive voltage
摘要: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors (P1, N1) before the gate terminals of each switching (P2, N2). Each has a terminal coupled shield (Vshld) magnitude substantially midway between ground potential and positive voltage. The signal conveyed source-drain channel transistor.