High voltage cmos logic using low voltage cmos process

作者: Richard Alexander Erhart

DOI:

关键词: Pass transistor logicGround bounceStatic induction transistorField-effect transistorElectrical engineeringMultiple-emitter transistorEngineeringDrain-induced barrier loweringThreshold voltageOverdrive voltage

摘要: CMOS transistor logic circuitry is permitted to operate at higher power supply voltages while retaining lower voltage processing geometries by inserting input shielding transistors (P1, N1) before the gate terminals of each switching (P2, N2). Each has a terminal coupled shield (Vshld) magnitude substantially midway between ground potential and positive voltage. The signal conveyed source-drain channel transistor.

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