Apparatus and method for controlling storage access in a multilevel storage system
作者： Philip Lewis Rosenfeld
DOI:
关键词: Cache 、 Linked list 、 Computer hardware 、 Computer data storage 、 Digital data processing 、 Computer science 、 Instruction unit 、 Offset (computer science) 、 CPU cache
摘要: In a digital data processing system including an Instruction Unit, Execute and multilevel Processor Storage System cache memory, additional apparatus is included referred to as Load Control Block Address Unit for implementing load control block address instruction which permits prefetching of from main memory into simultaneous with execution sequence instructions in linked list wherein information determining starting next the stored at location current fixed offset beginning block.
lens.org 参考文章(7)
Richard J Tobias, Data processing system with variable prefetch and replacement algorithms ,(1973)
Charles P. Ryan, Marion G. Porter, Cache apparatus for enabling overlap of instruction fetch operations ,(1978)
William E. Hall, Instruction cache memory system ,(1983)
Andrew B. McNeill, Gerald A. Marazas, Gerald U. Merckel, Jerry D. Dixon, Automatic adjustment of the quantity of prefetch data in a disk cache operation ,(1981)
Arnold Richard F, Wlerzbicki John R, Robelen Russel J, Dauber Philip S, Freiman Charles, Interstorage transfer mechanism ,(1969)
Kenichi Wada, Kanji Kubo, Data processing system with data cross-block-detection feature ,(1980)