Acceleration of k-Nearest Neighbor Algorithm on FPGA using Intel SDK for OpenCL

摘要: Field Programmable Gate Arrays (FPGAs) have been widely used for accelerating machine learning algorithms. However, the high design cost and time implementing FPGA-based accelerators using traditional HDL-based methodologies has discouraged users from designing accelerators. In recent years, a new CAD tool called Intel FPGA SDK OpenCL (IFSO) allowed fast efficient of hardware level specification such as OpenCL. Even software engineers with basic knowledge could this paper, IFSO to explore acceleration k-Nearest-Neighbor (kNN) algorithm FPGAs. kNN is popular in learning. Bitonic sorting was within check if provides any performance improvements. The experimental results obtained were compared state art CPU implementation. optimized implemented on two different FPGAs (Intel Stratix A7 Arria 10 GX). Experimental show that provided similar or better execution (up 80X faster) power efficiency (83% reduction consumption) than platforms workstation based Xeon processors E5-2620 Series (each 6 cores running at 2.4 GHz).