High-Performance Pipelined Architecture for Tree-Based IP Lookup Engine on FPGA

摘要: IP lookup problem involves searching the input address for a matching prefix in routing table. Hardware-accelerated engines based on various data structures such as balanced tree have been proposed over years. In tree-based approaches, size of increases, large off-chip memory has to be used. addition, linear growth wire length with respect number nodes at level adversely affects throughput. We present engine FPGA which optimizes pipeline scalability and Our solution following novel features: (1) 2-dimensional fine-grained layout Processing Elements (PEs) using distributed RAM reduce maximum length. (2) employ "split-tree" architecture BRAM-based PEs each improve clock rate. (3) use realistic model access guarantee high throughput process. Post place-and-route results show that, our can achieve 400MLPS (million lookups per second) any table containing 256~512K IPv6 prefixes, while 59% logic resources 19% BRAM available state-of-the-art device.