Page allocation to reduce access time of physical caches

摘要: A simple modification to an operating system''s page allocation algorithm can give physically addressed caches the speed of virtually caches. Colored reduces number bits that need be translated before cache access, allowing large low-associativity indexed address translation, which latency processor. The colored also has other benefits: miss less (in general) and more uniformly, inclusion principle holds for second level with associativity. However, requires main memory partitioning, common shared virtual addresses. Simulation results show high non-uniformity rates normal allocation. Analysis demonstrates extent second-level inclusion, reduction in effective main-memory due partitioning.