Data processing modules requiring different average clock frequencies having a common clock and a clock gating circuit for deleting clock pulses applied to the modules at times consistent with data sourcing and sinking capabilities
作者： Paul Rowland
DOI:
关键词: Electronic engineering 、 Synchronous circuit 、 CPU multiplier 、 Clock signal 、 Word clock 、 Computer hardware 、 Clock skew 、 Clock domain crossing 、 Clock gating 、 Computer science 、 Digital clock manager
摘要: A method and apparatus are provided for docking data processing modules, which require differing average clock frequencies, transferring between the modules. This comprises a means providing common dock signal to Clock pulses deleted from individual modules in dependence on frequency required by each module. applied is be transferred at times consistent with transfer.
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