作者: Matthew Loh
DOI: 10.7907/FQ18-2X96.
关键词: Chip 、 Power budget 、 Adaptive equalizer 、 Electronic engineering 、 Data recovery 、 Modular design 、 Retiming 、 Scalability 、 Wireless 、 Engineering
摘要: The scalability of CMOS technology has driven computation into a diverse range applications across the power consumption, performance and size spectra. Communication is necessary adjunct to computation, whether this push data from node-to-node in high-performance computing cluster or receiver wireless link neural stimulator biomedical implant, interconnect can take up significant portion overall system budget. Although single methodology cannot address such broad systems efficiently, there are number key design concepts that enable good age highly-scaled CMOS: an emphasis on highly-digital approaches solving ‘analog’ problems, hardware sharing between links as well different functions (such equalization synchronization) same link, adaptive changes its operating parameters mitigate not only variation fabrication but also conditions change over time. These demonstrated through use two examples, at extremes A novel all-digital clock recovery technique for high-performance, high density been developed. Two independently adjustable phases generated delay line calibrated 2 UI. One phase placed middle eye recover data, while other swept line. samples produced by clocks compared generate information, which used determine best recovery. swapped after updated; ping-pong action allows infinite without PLL DLL. scheme's generalized sampling retiming architecture saves area high-density interconnect. information useful tuning equalizer, circumventing need dedicated adaptation hardware. On side performance/power spectra, capacitive proximity developed support 3D integration implants. In order integrate more functionality staying within limits, implant electronics be embedded onto foldable parylene (‘origami’) substrate. Many ICs origami will face-to-face with each other, so increase communication decreasing size, facilitate modular approach design, where pre-fabricated parylene-and-IC modules assembled together on-demand make custom Such needs able sense adapt alignment. proposed array uses TDC-like structure realize both alignment sensing set plates, increasing eliminating infer quality separate block. distinguish plates nearby ground plane, stimulus applied transmitter plate, rectified bias generation This turn converted digital word using TDC, providing information.