Method, apparatus and system for a per-dram addressability mode
作者： Kuljit Bains
DOI:
关键词: System bus 、 Dram 、 Memory controller 、 CAS latency 、 Addressability 、 Dynamic random-access memory 、 Computer hardware 、 Memory rank 、 Static random-access memory 、 Computer science
摘要: Techniques and mechanisms for programming an operation mode of a dynamic random access memory (DRAM) device. In embodiment, controller stores value in register DRAM device, the specifying whether per-DRAM addressability (PDA) device is enabled. An external contact coupled to via signal line data bus. another sends while PDA enabled, specify one or more features are programmable.
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