A New Switch Block for Segmented FPGAs
作者： M. Imran Masud , Steven J. E. Wilton
DOI: 10.1007/978-3-540-48302-1_28
关键词: Transistor 、 Computer science 、 Routing (electronic design automation) 、 Computer hardware 、 Block (telecommunications) 、 Field-programmable gate array 、 Embedded system
摘要: We present a new switch block for FPGAs with segmented routing architectures. show that the outperforms all previous blocks over wide range of architectures in terms area, virtually no impact on speed. For segments length four, our results an FPGA 13% fewer transistors fabric.
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acm.org 参考文章(5)
Steven JE Wilton, Architectures and algorithms for field-programmable gate arrays with embedded memory University of Toronto. ,(1997)
Vaughn Betz, Jonathan Rose, FPGA routing architecture Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays - FPGA '99. pp. 59- 68 ,(1999) , 10.1145/296399.296428
Jonathan Rose, Dwight Hill, Architectural and physical design challenges for one-million gate FPGAs and beyond field programmable gate arrays. pp. 129- 132 ,(1997) , 10.1145/258305.258324
Yao-Wen Chang, D. F. Wong, C. K. Wong, Universal switch modules for FPGA design ACM Transactions on Design Automation of Electronic Systems. ,vol. 1, pp. 80- 101 ,(1996) , 10.1145/225871.225886
J. Cong, Yuzheng Ding, FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 13, pp. 1- 12 ,(1994) , 10.1109/43.273754