Self aligning small scale integrated circuit semiconductor chips to form large area arrays

摘要: Small scale integrated chips are fabricated from a semiconductor wafer and subsequently pretested formed into large area arrays with self aligning locking characteristics due to the axial orientation of geometries employed for based upon orientation, whereby spacing abutting chip edges in an array may be less than 7 μm. The wafer, e.g., silicon wherein boundaries aligned vertical {111} planes crystalline material so that each defined within parallelogrammatic like by these their intersections. term "parallelogrammatic geometries" means all geometric shapes capable being various structure wafer. Examples such parallelograms aspect ratios variations or combinations planar figures composed parallelograms. Specific examples diamond shaped chevron configurations.