Hierarchical cache arrangement wherein the replacement of an LRU entry in a second level cache is prevented when the cache entry is the only inclusive entry in the first level cache
作者： Kimming So , Hoichi Cheong , Dwain A. Hicks
DOI:
关键词: Computer science 、 Cache coloring 、 Cache pollution 、 Cache algorithms 、 Cache invalidation 、 Cache 、 Parallel computing 、 Page cache 、 Pipeline burst cache 、 Smart Cache
摘要: The present invention provides balanced cache performance in a data processing system. system includes first processor, second memory, memory and control circuit. processor is connected to the which serves as level for processor. are Replacement of set results being invalidated memory. circuit prevents replacing from congruence class all sets that cache.
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