作者： K. M. Kavi , A. R. Hurson , H.-S. Kim
DOI:
关键词: Multithreading 、 Computer science 、 Signal programming 、 Architecture 、 Dataflow architecture 、 CAS latency 、 Dataflow 、 Scheduling (computing) 、 Instruction cycle 、 Parallel computing
摘要: Recent tronds in technology are widening the performance gap between memory and processors. Multithreading has been suggested as a possible solution to minimizing loss of CPU cycles due latency, by executing several instruction streams simultaneously. In this paper, we propose new multithreaded dataflow architecture that uses RISC-like pipelines control-flow-like scheduling instructions, but retains functional properties model. addition, our Scheduled Dataflow utilizes two separate hardware units for execution threads, decoupling accesses from pipeline execution. We present data obtained using queuing analyses proposed architecture. Our investigate impact fine-grained vs. coarse-grained number contexts,