Single-loop linear-exponential multi-bit incremental analog-to-digital converter
作者： Maloberti Franco , Martins Rui Paulo Da Silva , Sin Sai-Weng , Wang Biao
DOI:
关键词: Dynamic range 、 Voltage 、 Electronic engineering 、 Integrator 、 Analog-to-digital converter 、 Decimation 、 Adder 、 Exponential function 、 Linear phase 、 Computer science
摘要: An incremental analog-to-digital converter (IADC) with a two-phase linear-exponential accumulation loop for improving the signal to noise distortion ratio (SNDR) and dynamic range (DR) is disclosed. The IADC includes an analog modulator decimation filter. has input receiving voltage output. integrator, adder, quantizer, noise-coupling path, data weighted averaging (DWA) circuit, digital-to-analog (DAC). filter signals from output of modulator. 1st order accumulator, exponential decimator. configured operate linear phase suppressing thermal boosting SQNR.
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