Improving the Security of Dual-Rail Circuits

摘要: Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the consumption independent of processed data. Standard dual-rail uses a with single spacer, e.g. all-zeroes, which gives rise balancing problems. We address these problems incorporating two spacers; spacers alternate between adjacent clock cycles. This guarantees that all gates switch in each cycle regardless transmitted data values. To generate circuits an automated tool has been developed. It is capable converting synchronous netlists into it interfaced industry CAD tools. single-rail benchmarks based upon Advanced Encryption (AES) have simulated compared order evaluate method.