Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature

摘要: A computer system has a memory controller that includes read buffers coupled to plurality of channels. The advantageously eliminates the inter-channel skew caused by modules being located at different distances from controller. preferably channel interface and synchronization logic circuit for each channel. This write load unload pointers buffer. Unload pointer generates pointer. are free-running increment in accordance with two clock signals. increments generated but been routed out back modules. itself Because trace length may differ, time it takes module provide data differ “skew” is defined as difference between when arrives on earliest latest During initialization, synchronized. After used such way effects inner-channel eliminated.