CRIB

摘要: Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined execution lanes. This requires multiple structures repeated dependency resolution, imposing significant dynamic power overhead. paper advocates in-place instructions, power-saving, pipeline-free approach that consolidates rename, issue, bypass one structure---the CRIB---while simultaneously eliminating the need for multiported file, instead storing architected state in simple rank latches. CRIB achieves high IPC an out-of-order machine while keeping core clean, simple, low power. The datapath within structure is purely combinational, most clocked elements fully synchronous yet high-frequency design. Experimental results match cycle time baseline design reducing energy consumption by more than 60% affected structures.