作者: Nadia Nedjah , Luiza de Macedo Mourelle
DOI: 10.1007/978-3-319-03110-1_1
关键词: Reconfigurable computing 、 FpgaC 、 Computer science 、 Artificial neural network 、 Systolic array 、 Hardware architecture 、 Genetic algorithm 、 Genetic operator 、 Computation 、 Computer architecture
摘要: In this chapter,we propose a massively parallel architecture of hardware implementation genetic algorithms. This design is quite innovative as it provides viable solution to the fitness computation problem, which depends heavily on problem-specific knowledge. The proposed completely independent such specifics. It implements using neural network. used network stochastic and thus minimises required area without much increase in response time. Last but not least, we demonstrate characteristics compare existing ones.