作者: Laiqiang Luo , Kalya Shubhakar , Sen Mei , Nagarajan Raghavan , Binghai Liu
DOI: 10.1109/TDMR.2017.2787908
关键词: Particle-size distribution 、 Materials science 、 Optoelectronics 、 Annealing (metallurgy) 、 Transistor 、 Non-volatile memory 、 Grain growth 、 Silicon 、 Grain size 、 Static random-access memory
摘要: Polysilicon (poly-Si) grain size control is a critical issue with scaling of MOS transistors in integrated-circuit design, more so embedded nonvolatile memory (NVM) technology. This paper investigates an approach to suppress poly-Si growth under necessary additional thermal budget for 40-nm NVM Our studies reveal that carbon implant can and the dose rather than its energy plays key role controlling size. Physical analysis using advanced planar transmission electron microscopy technique shows reduction increasing dose. The application sub-40 nm technology therefore help reduce SRAM ${V} _{{MIN}}$ -related failures significantly. In this paper, we present complete process reliability case study incorporate as effective solution suppressing growth, thereby eliminating side effects NVM.