作者: Shirish Kumar Agarwal , Sravan Kumar Ambapuram , Krishna V.S.S.S.R. Vanka , Nikhil Kumar Kansal
DOI:
关键词: Network packet 、 Packet analyzer 、 Component (UML) 、 Processing delay 、 Computer hardware 、 Hardware acceleration 、 Frame (networking) 、 Fast packet switching 、 Real-time computing 、 Hardware register 、 Computer science
摘要: A method and computing apparatus for controlling operation of hardware processing components are disclosed. The may include receiving a data packet (e.g., media frame) at the device, with plurality to display packet, monitoring movement among components. time indication each component is generated that indicates when will be received, frequency adjusted based upon frame arrive processed.