Frame rate conversion with asynchronous pixel clocks

摘要: A frame rate conversion system synchronizes data transfers to and from a VRAM buffer which are concurrent, continuous, asynchronous. The comprises having split memory for communicating output shift register. control supervises writing operations the at first rate. display reading register second is slower than communicate signals through double synchronizers. has counter counting frames of have been read buffer. prevents into after particular number counted so as prevent over destroying existing not yet by control. Moreover, control, respectively, each time that skipped. Furthermore, causes transfer when horizontal blank deasserted within incoming analog video signal.