作者: Nimrod Alexandron , Alexander Rabinovitch , Leonid Dubrovin
DOI:
关键词: Physical address 、 Address bus 、 Computer science 、 Memory address register 、 Value (computer science) 、 Controller (computing) 、 Computer network 、 Computer hardware 、 Direct memory access 、 Access time
摘要: An apparatus having a memory and controller is disclosed. The may be configured to (i) receive read request from processor, the comprising first value second value, (ii) where an indirect access, (a) generate address in response (b) data stored at (c) data, (iii) direct (iv) requested address.