On-chip traffic prioritization in memory
作者： Bruce M. Fleischer , Ravi Nair , Hans M. Jacobson , Thomas W. Fox
DOI:
关键词: Uniform memory access 、 Flat memory model 、 Computer science 、 Memory refresh 、 Memory management 、 Interleaved memory 、 Semiconductor memory 、 Computer hardware 、 Registered memory 、 Memory map 、 Computer network
摘要: According to one embodiment, a method for traffic prioritization in memory device includes sending access request including priority value from processing element the crossbar interconnect device. The is routed through controller associated with request. received at controller. of compared values plurality requests stored queue determine highest A next performed by based on
lens.org 参考文章(14)
Dennis Abts, Fair Hierarchical Arbitration Of a Shared Resource With Varying Traffic Intensity ,(2012)
Jayaram Mudigonda, Jeffrey Clifford Mogul, Methods and apparatus to control generation of memory access requests ,(2011)
Vasundhara Gurunath, Kishore Kumar Muppirala, Senthil R. Kumar, Method and system for an improved i/o request quality of service across multiple host i/o ports ,(2011)
Kunle A. Olukotun, Cache crossbar arbitration ,(2004)
David R. Resnick, Error correction and recovery in chained memory architectures ,(2013)
Jaewoong Chung, Memory request scheduling based on thread criticality ,(2010)
Andrew Dunshea, Jos Manuel Accapadi, Mark Elliot Hack, Matthew Accapadi, Mysore Sathyanarayana Srinivas, Augustin Mena, Scheduling threads in a multiprocessor computer ,(2008)
Karthick Rajamani, William E. Speight, Lixin Zhang, John B. Carter, Jian Li, Instruction set architecture extensions for performing power versus performance tradeoffs ,(2010)
Hongzhong Zheng, Jiang Lin, Zhao Zhang, Zhichun Zhu, Memory Access Scheduling Schemes for Systems with Multi-Core Processors international conference on parallel processing. pp. 406- 413 ,(2008) , 10.1109/ICPP.2008.53
Wael R. El-Essawy, Lixin Zhang, Thread completion rate controlled scheduling ,(2008)