Architecture for high speed class of service enabled linecard

摘要: A linecard architecture for high speed routing of data in a communications device. This provides low latency based on packet priority: and processing occurs at line rate (wire speed) most operations. stream is input to the inbound receiver, which uses small FIFO rapidly accumulate bytes. Once header portion received, alone used perform lookup modification. The queue manager then class service information enqueue according required priority. Enqueued packets are buffered large memory space holding multiple prior transmission across device's switch fabric outbound linecard. On arrival linecard, enqueued transmitter architecture. Another large, multi-packet structure, as employed manager, buffering onto network.