High-speed test system for a memory device

摘要: A memory device requires a minimum of two input/output lines from an external testing to be coupled thereto. first DQ line the provides direct data path array so that tester can read at maximum speed device. Test mode circuitry for multiplexing and comparing multiple during address compression is or more lines, including line. The include on-chip comparators compare simultaneously written to, from, comparison outputs test flag indicating whether not matches. output through multiplexer second As result, tested line, while results sampled compares only bits given word, but also least one bit another word. Therefore, rather than employing circuits words, third circuit circuits, present invention avoids need by word in with