Matrix multiplication by an inexact systolic array

摘要: Different schemes for approximate computing of matrix multiplication (MM) in systolic arrays are presented this manuscript. Inexact full adder cells utilized a processing element (PE) the Baugh-Wooley multiplier and/or final as circuits implementing two computational steps required MM. An extensive analysis and simulation-based assessment three inexact PE pursued with respect to circuit level performance (such delay, power consumption number transistors) figures merit error distance). The execution MM each results an computation affecting only outputs same columns, so extension array can also be performed very limited error. discrete cosine transform application proposed arrays, is evaluated; simulation show that effective, incurring small