Architecture and method for cache-based checkpointing and rollback
作者： David Paul Campagna , David J. Kessler , David R. Bueno
DOI:
关键词: Mode (computer interface) 、 Cache 、 Rollback 、 Architecture 、 Computer science 、 Multi-core processor 、 Parallel computing
摘要: A cache system to compare memory transactions while facilitating checkpointing and rollback is provided. The includes at least one processor core including operating in write-through mode, two checkpoint caches write-back a comparison/checkpoint logic, main memory. are communicatively coupled the mode. logic caches. compares stored responsive an initiation of checkpointing.
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