High speed divider with square root capability

作者: Tony Hurson , Salim A. Shah , Stephen D. McIntyre , Ken Tseng , Thomas W. Lynch

DOI:

关键词: MultipleDivision (mathematics)QuotientRemainderSquare rootOperandMathematicsArithmeticSeries (mathematics)

摘要: An apparatus for performing the division of a first operand by second iteratively producing series partial remainders and predicted quotient bits utilizing generation multiples selection one generated multiples. The is selected as remainder. A bit from operands next remainder operand. One based upon prediction. then produced multiple

参考文章(8)
Thomas H. Howell, Charles W. Ferrell, Division by a constant by iterative table lookup ,(1985)
Richard George Allen, Donald Lee Freerksen, Two-bit floating point divide circuit with single carry-save adder ,(1990)
Michael C. Gill, Henry M. Darley, Maria B. L. Hipona, Paul C. Wang, Dinh T. Ngo, Dale C. Earl, Jim Dodrill, Floating point/integer processor with divide and square root functions ,(1989)
Suren Irukulla, Bimal V Patel, Method and apparatus for numerical division ,(1986)
M. Birman, A. Samuels, G. Chu, T. Chuk, L. Hu, J. McLeod, J. Barnes, Developing the WTL3170/3171 Sparc floating-point coprocessors IEEE Micro. ,vol. 10, pp. 55- 64 ,(1990) , 10.1109/40.46769