A 25 Gb/s All-Digital Clock and Data Recovery Circuit for Burst-Mode Applications in PONs

摘要: The upcoming 100 Gb/s links in the next-generation ethernet passive optical networks will be based on four channels of 25 Gb/s. corresponding transceivers these require a high-speed clock and data recovery circuit to extract synchronous recover received data. To achieve sufficiently fast settling time for 25 Gb/s burst mode upstream applications (PONs), we introduce an architecture first all-digital (AD-CDR). Thanks implementation digital loop filter, our AD-CDR avoids need system or start-of-burst signal. This is implemented 40-nm CMOS process has very compact active chip area only 0.050 mm $^2$ . Furthermore, performance burst-mode operation setup measured reported, resulting lock 37.5 ns consuming 46 mW.