3D chip with shielded clock lines

摘要: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated (IC) dies to at least partially overlap and share one interconnect layers distribute power, clock and/or data-bus signals. The shared include segments carry In some embodiments, are higher level (e.g., top layer each IC die). stacked 3D first second dies. die includes semiconductor substrate set defined above substrate. Similarly, As further described below, in placed face-to-face arrangement vertically arrangement) has facing other. subset wiring carries signals supplied die.