作者: Hanjun Kim , Seungbin Song , Heelim Choi
DOI: 10.1109/CGO51591.2021.9370309
关键词: Cycles per instruction 、 Software 、 Packet processing 、 Compiler 、 Pipeline (software) 、 Networking hardware 、 Computer science 、 Synchronization (computer science) 、 Public switched data network 、 Parallel computing
摘要: Network programming languages enable programmers to implement new network functions on various hardware and software stacks in the domain of Software Defined Net-working (SDN). Although extend flexibility devices, existing compilers do not fully optimize programs due their coarse-grained parallelization methods. The consider each packet processing table that consists match action as a unit tasks parallelize without decomposing functions. This work proposes fine-grained pipeline compiler for languages, named PSDN. First, PSDN decouples from tables analyzes dependencies among matches actions. While respecting dependencies, efficiently schedules function into with clock cycle estimation fuses reduce synchronization overheads. implements translates P4 program Xilinx PX program, which is synthesizable NetFPGA-SUME hardware. proposed reduces latency by 12.1 % utilization 3.5 compared previous work.