Dram variable row select
作者： Michael C. Parris
DOI:
关键词: Flat memory model 、 Memory address register 、 Memory refresh 、 Address bus 、 Controller (computing) 、 Physical address 、 Computer hardware 、 Dram 、 Computer science 、 Address decoder
摘要: A memory device circuit that alters the input refresh addresses to access fewer cells save power, or address more decrease time. The contains a simple transistor configuration blocks certain bits, then substitutes active bits in their place decoder. also includes controller is responsive entering mode. When used mode, may be passed unblocked decoder for full user control.
lens.org 参考文章(3)
Emiko Iizuka, Shuzo Nakajima, Memory refresh control system upon connection of extension unit. ,(1992)
Takahiro Komatsu, Yasuhiro Konishi, Youichi Tobita, Katsumi Dosaka, Masaki Kumanoya, Semiconductor memory device improved for externally designating operation mode ,(1990)