Invariant Checking Combining Forward and Backward Traversal

作者: Christian Stangier , Thomas Sidle

DOI: 10.1007/978-3-540-30494-4_29

关键词: Binary decision diagramInvariant (mathematics)ComputationRedundancy (engineering)AlgorithmFormal methodsTree traversalComputer scienceCircuit designInterleaving

摘要: In invariant checking two directions of state space traversal are possible: Forward from initial states or backward starting potential error states. It is not clear in advance, which direction will be computationally easier terminate fewer steps. This paper presents a dynamic approach based on OBDDs for interleaving forward and traversal. The increases the chance selecting shorter at same time limits overhead due to redundant computation. Additionally, second using with different variable orders presented, providing improved completion cost some additional overhead. These approaches result dramatic gain efficiency over unidirectional For first all benchmarks VIS-Verilog suite have been finished BDD-based method.

参考文章(12)
Edmund M. Clarke, David E. Long, Jerry R. Burch, Symbolic Model Checking with Partitioned Transistion Relations. IEEE Transactions on Very Large Scale Integration Systems. pp. 49- 58 ,(1991)
Philip R. Moorby, Donald E. Thomas, The Verilog® Hardware Description Language ,(1990)
Steven Fortune, John Hopcroft, Erik Meineche Schmidt, The Complexity of Equivalence and Containment for Free Single Variable Program Schemes international colloquium on automata, languages and programming. pp. 227- 240 ,(1978) , 10.1007/3-540-08860-1_17
Matthew Hennessy, Robin Milner, On Observing Nondeterminism and Concurrency international colloquium on automata, languages and programming. pp. 299- 309 ,(1980) , 10.1007/3-540-10003-2_79
Gianpiero Cabodi, Sergio Nocco, Stefano Quer, Mixing Forward and Backward Traversals in Guided-Prioritized BDD-Based Verification computer aided verification. pp. 471- 484 ,(2002) , 10.1007/3-540-45657-0_38
Robert K. Brayton, Gary D. Hachtel, Alberto Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz, Szu -Tsung Cheng, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, Abelardo Pardo, Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Staple, Gitanjali Swamy, Tiziano Villa, VIS: A System for Verification and Synthesis computer aided verification. pp. 428- 432 ,(1996) , 10.1007/3-540-61474-5_95
G. Cabodi, P. Camurati, S. Quer, Efficient state space pruning in symbolic backward traversal international conference on computer design. pp. 230- 235 ,(1994) , 10.1109/ICCD.1994.331895
Shankar G. Govindaraju, David L. Dill, Verification by approximate forward and backward reachability international conference on computer aided design. pp. 366- 370 ,(1998) , 10.1145/288548.289055
Olivier Coudert, Christian Berthet, Jean Christophe Madre, Verification of synchronous sequential machines based on symbolic execution computer aided verification. ,vol. 407, pp. 365- 373 ,(1989) , 10.1007/3-540-52148-8_30
Bryant, Graph-Based Algorithms for Boolean Function Manipulation IEEE Transactions on Computers. ,vol. 35, pp. 677- 691 ,(1986) , 10.1109/TC.1986.1676819