Simulation-based validation of VHDL descriptions using constraints logic programming
作者： Laurent Capocchi , Marie-Laure Nivet , Fabrice Bernardi , Christophe Paoli , Umr Cnrs
DOI:
关键词: Software testing 、 Test (assessment) 、 Simulation based 、 Code (cryptography) 、 Logic programming 、 Programming language 、 Computer science 、 VHDL
摘要: This paper presents a simulation based validation approach for test vectors generation. We suggest to borrow techniques used successfully in the software testing and constraints logic programming areas. Our methodology is on three following steps: VHDL code modeling analysis, constraints-based stimuli generation sequences
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