SynchronizationCoherence:ATransparentHardwareMechanismfor CacheCoherenceandFine-GrainedSynchronization

摘要: The quest to improve performance forces designers explore flner-grained multiprocessor machines. Ever increasing chip densities based on CMOS improvements fuel research in highly parallel multiprocessors with 100s of processing elements. With such levels parallelism, synchronization is set become a major bottleneck and e‐cient support for an important design criterion. Previous has shown that integrating flne-grained can have signiflcant beneflts compared traditional coarse-grained synchronization. Not much progress been made supporting transparently processor nodes: key reason perhaps why wide adoption not followed. In this paper, we propose novel approach called Synchronization Coherence provide transparent flnegrained caching machine single-chip multiprocessor. Our merges mechanisms cache coherence protocols. It reduces network utilization as well related overheads while adding minimal hardware complexity or previously reported techniques. addition its beneflt making nodes, the applications studied, it provides up 23% improvement 24% energy e‐ciency no L2 caches previous increases 38% when simulating ideal system.