Design-oriented characterization of CMOS over the continuum of inversion level and channel length

摘要: A methodology for small signal characterization of CMOS processes over the full range inversion level and channel length is presented. Measured transconductance output conductance a 0.5 /spl mu/m standard process are presented from deep weak to strong both NMOS PMOS devices lengths ranging 33.4 mu/m. The data in normalized form permitting device evaluation at any level, length, drain current. This useful modern analog design anywhere continuum length. method furthermore presents novel rigorous benchmark evaluating accuracy compact MOS models. Initial results given illustrating EKV model accuracy. can be extended deeper submicron addressing increasing uncertainty parameter values