Low-jitter loop filter for a phase-locked loop system
作者： Melvin L. Hagge , Baker Scott , Adrian Maxim , Edmund M. Schneider
DOI:
关键词: Delay-locked loop 、 Linear circuit 、 Phase-locked loop 、 Control theory 、 Phase (waves) 、 Frequency multiplier 、 Path (graph theory) 、 Signal 、 Charge pump 、 Mathematics
摘要: A loop filter device and method for implementing a phase locked (“PLL”) circuit, which locks frequency of signal to reference frequency, are disclosed. The includes proportional path circuit an integral circuit. receives charge pump output determines holds be directed or taken from PLL throughout update period based on detected difference the locking frequency. is coupled another tracks total level differences present prior periods.
lens.org 参考文章(15)
I.I. Novof, J. Austin, R. Kelkar, D. Strayer, S. Wyatt, Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter international solid-state circuits conference. ,vol. 30, pp. 1259- 1266 ,(1995) , 10.1109/4.475714
John George Maneatis, Phase-locked loop with conditioned charge pump output ,(2002)
W. Rhee, Design of high-performance CMOS charge pumps in phase-locked loops international symposium on circuits and systems. ,vol. 2, pp. 545- 548 ,(1999) , 10.1109/ISCAS.1999.780807
Russell W. Brown, Dual-charge-pump bandwidth-switched phase-locked loop ,(1991)
Joonsuk Lee, Beomsup Kim, A low-noise fast-lock phase-locked loop with adaptive bandwidth control IEEE Journal of Solid-state Circuits. ,vol. 35, pp. 1137- 1145 ,(2000) , 10.1109/4.859502
Li Lin, L. Tee, P.R. Gray, A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture international solid-state circuits conference. pp. 204- 205 ,(2000) , 10.1109/ISSCC.2000.839750
A. Maxim, M. Gheorghe, A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation international symposium on circuits and systems. ,vol. 5, pp. 511- 514 ,(2001) , 10.1109/ISCAS.2001.922097
J.G. Maneatis, Low-jitter and process independent DLL and PLL based on self biased techniques international solid-state circuits conference. ,vol. 31, pp. 1723- 1732 ,(1996) , 10.1109/JSSC.1996.542317
D. Mijuskovic, M. Bayer, T. Chomicz, N. Garg, F. James, P. McEntarfer, J. Porter, Cell-based fully integrated CMOS frequency synthesizers custom integrated circuits conference. ,vol. 29, pp. 271- 279 ,(1993) , 10.1109/4.278348
Charles J. Masenas, Anthony J. Perri, Troy A. Seman, Fractional integration and proportional multiplier control to achieve desired loop dynamics ,(2001)