Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor—the DEC Alpha 21264 microprocessor

摘要: DIGITAL's Alpha 21264 processor is a highly out-of-order, superpipelined, superscalar implementation of the architecture, capable peak execution rate six instructions per cycle and sustainable four cycle. The also features 500 MHz clock speed high-bandwidth system interface that channels up to 5.3 Gbytes/second cache data 2.6 main-memory into processor. Simulation-based functional verification was performed on logic design using implementation-directed, pseudo-random exercisers, supplemented with implementation-specific, hand-generated tests. Extensive coverage analysis grade direct effort. success effort underscored by first prototype chips which were used boot multiple operating systems across several different systems.