Block address translation circuit using two-bit to four-bit encoder
作者： David James Martens , Terence Matthew Potter
DOI:
关键词: Page address register 、 Encoder 、 Computer hardware 、 Virtual address space 、 Address bus 、 Memory address register 、 Physical address 、 Computer science 、 Logical address 、 Address space
摘要: An approach for determining whether a current address is within an range in which both the starting of and size are determined by variable register contents. Whereas information contents binary format, 2B format. The present invention provides logic translating formatted so that it can be compared to address.
google.de 参考文章(8)
Steve J. Ciavaglia, Joseph T. Scanlon, Peter Y. Hsu, Variable page size translation lookaside buffer ,(1993)
John Zolnowsky, Michael W. Cruess, William C. Moyer, Paged memory management unit which evaluates access permissions when creating translator ,(1988)
Brad Beavers, Pei-Chun Liu, Chua-Eoan Lew, Chih-Jui Peng, Address translator and method of operation ,(1994)
William M. Keshlear, John Zolnowsky, William C. Moyer, Paged memory management unit having variable number of translation table levels ,(1985)
Chih-Jiu Peng, Paul C. Rossbach, Address translation circuit ,(1994)
Younes Lotfi, Array row and column decoder apparatus and method ,(1997)
David B. Papworth, Andrew F. Glew, Michael Alan Fetterman, Robert P. Colwell, Frederick Jay Pollack, Glenn J. Hinton, Methods and apparatus for determining operating characteristics of a memory element based on its physical location ,(1996)