Scalable shader architecture

摘要: A scalable shader architecture is disclosed. In accord with that architecture, a includes multiple pipelines, each of which can perform processing operations on rasterized pixel data. Shader pipelines be functionally removed as required, thus preventing defective pipeline from causing chip rejection. The distributor processes data and then selectively distributes the processed to various beneficially in manner balances workloads. collector formats outputs into proper order form shaded instruction processor (scheduler) programs individual their intended tasks. Each has gatekeeper interacts such passes through controlled required.