Impact of nanowire variability on performance and reliability of gate-all-around III-V MOSFETs

作者: SH Shin , M Masuduzzaman , JJ Gu , MA Wahab , N Conrad

DOI: 10.1109/IEDM.2013.6724582

关键词: PlanarMOSFETStress (mechanics)NanowireFabricationMaterials scienceOptoelectronicsElectronic engineeringScalingReliability (semiconductor)Transistor

摘要: Gate-all-around (GAA) transistors use multiple parallel nanowires to achieve the desired ON current. The fabrication and performance of GAA have been reported, however, a fundamental consideration, namely, scaling variability transistor as function number NWs is yet be discussed. In this paper, we (i) examine how overall matrix (e.g., ION, IOFF, Vth, SS, RC) depends on NWs, (ii) theoretically interpret results in terms self-heating among (iii) compare reliability NW devices (ΔVth, ΔSS, both stress recovery) with planar device similar technology. We find that NW-to-NW are reflected novel properties neither anticipated nor observed corresponding

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