Customized architectures for faster route finding in GPS-based navigation systems

作者: Jason Loew , Dmitry Ponomarev , Patrick H. Madden

DOI: 10.1109/SASP.2010.5521148

关键词: SpeedupTurn-by-turn navigationPriority queueGlobal Positioning SystemMulti-core processorComputer scienceReal-time computingDijkstra's algorithmMobile deviceNavigation system

摘要: GPS based navigation systems became popular in dedicated handheld devices, and are now also found modern cell phones, other small personal devices. A key element of any system is fast effective route finding, this depends heavily on Dijkstra's shortest path algorithm. algorithm serial nature; prior efforts to accelerate it through parallel processing have had almost no success. In paper, we present a practical approach extract small-scale parallelism by shifting priority queue operations secondary tightly-coupled processor. We obtain substantial speedup real-world graphs (in particular, road maps), allowing the development that more responsive, lower total power consumption.

参考文章(23)
J. Renau, K. Strauss, L. Ceze, Wei Liu, S.R. Sarangi, J. Tuck, J. Torrellas, Energy-Efficient Thread-Level Speculation IEEE Micro. ,vol. 26, pp. 80- 91 ,(2006) , 10.1109/MM.2006.11
Boris V. Cherkassky, Craig Silverstein, Andrew V. Goldberg, Buckets, heaps, lists, and monotone priority queues symposium on discrete algorithms. pp. 83- 92 ,(1997) , 10.5555/314161.314187
Divya Gulati, Doug Burger, Stephen W. Keckler, Changkyu Kim, Simha Sethumadhavan, M.S. Govindan, Nitya Ranganathan, The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration international symposium on microarchitecture. pp. 394- 406 ,(2007) , 10.1109/MICRO.2007.41
Mark D. Hill, Michael R. Marty, Amdahl's Law in the Multicore Era IEEE Computer. ,vol. 41, pp. 33- 38 ,(2008) , 10.1109/MC.2008.209
Ravi Rajwar, James R. Goodman, Transactional lock-free execution of lock-based programs Tenth international conference on architectural support for programming languages and operating systems on Proceedings of the 10th international conference on architectural support for programming languages and operating systems (ASPLOS-X) - ASPLOS '02. ,vol. 36, pp. 5- 17 ,(2002) , 10.1145/605397.605399
M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt, Accelerating critical section execution with asymmetric multi-core architectures Proceeding of the 14th international conference on Architectural support for programming languages and operating systems - ASPLOS '09. ,vol. 44, pp. 253- 264 ,(2009) , 10.1145/1508244.1508274
Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke, Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications high-performance computer architecture. pp. 25- 36 ,(2007) , 10.1109/HPCA.2007.346182
Maurice Herlihy, J. Eliot B. Moss, Transactional memory Proceedings of the 20th annual international symposium on Computer architecture - ISCA '93. ,vol. 21, pp. 289- 300 ,(1993) , 10.1145/165123.165164
Michael Garland, Sparse matrix computations on manycore GPU's Proceedings of the 45th annual conference on Design automation - DAC '08. pp. 2- 6 ,(2008) , 10.1145/1391469.1391473