作者: Willy Jules Caesar Gruwez , Mustapha El Haddouchi , Koen Van Renterghem , Jan Robert Magdalena Codenie , Chris Coene
DOI:
关键词: Digital signal 、 Predistortion 、 Clock skew 、 Clock domain crossing 、 Self-clocking signal 、 Digital clock manager 、 Engineering 、 Synchronous circuit 、 Electronic engineering 、 Clock signal
摘要: Methods and systems to reduce clock spurs produced by a direct-RF modular acceptable levels using digital predistortion compensation signal. The signal may be used generate sine wave in the domain with adjustable phase amplitude. added processor (DSP) section of an upconvertor, combined undesired spur it or even cancel out completely. In some implementations, have similar level such that when spur, results having reduced